write32(0x43f00040, 0x00000000);
write32(0x43f00044, 0x00000000);
write32(0x43f00048, 0x00000000);
write32(0x43f0004C, 0x00000000);
write32(0x43f00050, 0x00000000);

write32(0x43f00000, 0x77777777);
write32(0x43f00004, 0x77777777);

write32(0x53f00040, 0x00000000);
write32(0x53f00044, 0x00000000);
write32(0x53f00048, 0x00000000);
write32(0x53f0004C, 0x00000000);
write32(0x53f00050, 0x00000000);

write32(0x53f00000, 0x77777777);
write32(0x53f00004, 0x77777777);

//;cs0
write32(0xB8002008, 0x00010000);
write32(0xB8002004, 0x00210511);
write32(0xB8002000, 0x00000200);

//;cs5
write32(0xB8002054, 0x00000001);
write32(0xB8002050, 0x00000200);

//cs1
write32(0xB8002018, 0x00010000);
write32(0xB8002010, 0x00000200);
write32(0xB8002014, 0x00210511);

//////
// Clock registers
//write32(0x53f80008, 0x2003C000);
write32(0x53f80008, 0x5003C000);
//write32(0x53f80008, 0x2003400);
write32(0x43fac454, 0x1000);

//cs4
write32(0xB8002040, 0x0000DCF6 );
write32(0xB8002044, 0x444A4541 );
write32(0xB8002048, 0x44443302 );

// Set ODT = 0
write32(0xB400000C, 0x0400);

//write32(0xB8002008, 0x0);
//write32(0xB8002004, 0x00200501);
//write32(0xB8002000, 0x00000800);

write32(0xd8002000, 0x0000CC03);
write32(0xd8002004, 0xa0330D01);
write32(0xd8002008, 0x00220800);

//DDR2 initial begin
//write32(0xB8001004, 0x007ffcff);
write32(0xB8001004, 0x0076E83a);
 
//  ESD_MISC 
//write32(0xB8001010, 0x0000020C);
// write32(0xB8001018, 0x0000004C);
write32(0xB8001010, 0x00000204);
 
//  ESD_ESDCTL0  SDE_SMODE_SP_ROW_00_COL_00_DSIZ_SREFR_0_PWDT_0_FP_BL_0__PRCT
//  ESD_ESDCTL0 32'b1_001__0__010_00__01_00___00___000_0___00_0__0__0_0_00000
//  enable CS0 precharge command 
write32(0xB8001000, 0x92210000);
 
//  precharge all dummy write only address matter
write32(0x80000f00, 0x12344321);
 
// ESD_ESDCTL0 : select Load-Mode-Register mode
write32(0xB8001000, 0xB2210000);
// DDR2 : Load reg EMR2
write8(0x82000000, 0xda);
// DDR2 : Load reg EMR3
write8(0x83000000, 0xda);
// DDR2 : Load reg EMR1 -- enable DLL
write8(0x81000400, 0xda);
// DDR2 : Load reg MR -- reset DLL
write8(0x80000333, 0xda);

// ESD_ESDCTL0 : select Prechare-All mode
write32(0xB8001000, 0x92210000);
// DDR2 : Prechare-All
write8(0x80000400, 0x12);

// ESD_ESDCTL0 : select Manual-Refresh mode
write32(0xB8001000, 0xA2210000);
// DDR2 : Manual-Refresh 2 times
write32(0x80000000, 0x87654321);
write32(0x80000000, 0x87654321);

// ESD_ESDCTL0 : select Load-Mode-Register mode
write32(0xB8001000, 0xB2210000);
// DDR2 : Load reg MR -- CL=3, BL=8, end DLL reset
write8(0x80000233, 0xda);
// DDR2 : Load reg EMR1 -- OCD default
write8(0x81000780, 0xda);
// DDR2 : Load reg EMR1 -- OCD exit
write8(0x81000400, 0xda);
 
//  ESD_ESDCTL0  SDE_SMODE_SP_ROW_00_COL_00_DSIZ_SREFR_0_PWDT_0_FP_BL_0__PRCT
//  ESD_ESDCTL0 32'b1_000__0__010_00__10_00___10___011_0___00_0__0__0_0_000000
//  @// normal mode row=010//col=10//dzize=10//self ref=011//PWDT =00//BL =0//prct =000000
 
write32(0xB8001000, 0x82216080);

// Init IOMUXC_SW_PAD_CTL_GRP_DDRTYPE_GRP(1-5)
write32(0x43FAC454, 0x00001000);

//WD
write16(0x53fdc000, 0x0033);
//comment clock gating open
//write32(0x53F8000C, 0xffffffff);
//write32(0x53F80010, 0xffffffff);
//write32(0x53F80014, 0xffffffff);