For those unfamiliar with OpenRISC, it is an open-source RISC/DSP processor
architecture. OpenCores.org makes available an implementation of this
architecture that can be synthesized, for example, as part of an FPGA or ASIC.
The port of eCos to OpenRISC was sponsored by the Rosum Corporation.
A few notes and caveats about the eCos OpenRISC port:
- The only platform supported at this time is ORP (OpenRISC Reference
Platform).
- The only ORP devices supported so far are serial ports used for
diagnostic and debugging purposes and AM29LVxxxx Flash ROM.
- To build and debug, you must build the GNU development tools from
source
available at the OpenCores web site -- not the versions available
from the GNU web site or elsewhere. There is a shell script in this directory that
will assist in downloading and building the GNU toolchain.
- For debugging, you can use either gdb's JTAG target or the serial
target. The latter has some advantages, e.g. the gdb serial target is
thread-aware, but it is much slower, especially while simulating.
Scott Furman
sfurman at rosum dot com